The Cache Coherence Problem in Shared-Memory Multiprocessors
Software Solutions
Systems
1. Auflage Januar 1996
358 Seiten, Softcover
Wiley & Sons Ltd
Almost all software solutions are developed through academic
research and implemented only in prototype machines leaving the
field of software techniques for maintaining the cache coherence
widely open for future research and development. This book is a
collection of all the representative approaches to software
coherence maintenance including a number of related efforts in the
performance evaluation field.
The book presents a selection of 27 papers dealing with
state-of-the-art software solutions for cache coherence maintenance
in shared-memory multiprocessors. It begins with a set of four
introductory readings that provides a brief overview of the cache
coherence problem and introduces software solutions to the problem.
The text defines and illustrates static and dynamic software
schemes, techniques for modeling performance evaluation mechanisms,
and performance evaluation studies.
The book is intended for the experienced reader in computer
engineering but possibly a novice in the topic of cache coherence.
It also provides an in-depth understanding of the problem as well
as a comprehensive overview for multicomputer designers, computer
architects, and compiler writers. In addition, it is a software
coherence reference handbook for advanced undergraduate and typical
graduate students in multiprocessing and multiprogramming areas.
Introduction.
Chapter 1: Introductory Readings.
How to Make a Multiprocessor Computer that Correctly Executes
Multiprocess Programs (L. Lamport).
Synchronization, Coherence, and Event Ordering in Multiprocessors
(M. Dubois, C. Scheurich, and F.A. Briggs).
Cache Coherence in Large-Scale Shared-Memory Multiprocessors:
Issues and Comparisons (D. Lilja).
Software Cache Consistency in Shared-Memory Multiprocessors: A
Survey of Approaches and Performance Evaluation Studies (I.
Tartalja and V. Milutinovic).
Chapter 2: Static Software Cache Coherence Schemes.
Compiler-Directed Cache Management in Multiprocessors (H. Cheong
and A.V. Veidenbaum).
RP3 Processor-Memory Element (W.C. Brantley, K.P. McAuliffe, and J.
Weiss).
A Compiler-Assisted Cache Coherence Solution for Multiprocessors
(A.V. Veidenbaum).
A Cache Coherence Scheme With Fast Selective Invalidation (H.
Cheong and A.V. Veidenbaum).
Automatic Management of Programmable Caches (R. Cytron, S.
Karlovsky, and K.P. McAuliffe).
A Version Control Approach to Cache Coherence (H. Cheong and A.V.
Veidenbaum).
Design and Analysis of a Scalable Cache Coherence Scheme Based on
Clocks and Timestamps (S.L. Min and J.-L. Baer).
A Generational Algorithm to Multiprocessor Cache Coherence (T.C.
Chiueh).
Cache Coherence Using Local Knowledge (E. Darnell and K.
Kennedy).
Chapter 3: Dynamic Software Cache Coherence Schemes.
Software-Controlled Caches in the VMP Multiprocessor (D.R.
Cheriton, G.A. Slavenburg, and P.D. Boyle).
CPU Cache Consistency with Software Support and Using "One Time
Identifiers" (A.J. Smith).
An Approach to Dynamic Software Cache Consistency Maintenance Based
on Conditional Invalidation (I. Tartalja and V. Milutinovic).
Adaptive Software Cache Management for Distributed Shared Memory
Architectures (J.K. Bennett, J.B. Carter, and W. Zwaenepoel).
Chapter 4: Techniques for Modeling and Performance Evaluation of
Cache Memories and Cache Coherence Maintenance Mechanisms.
Analysis of Multiprocessors with Private Cache Memories (J.H.
Patel).
Effectiveness of Private Caches in Multiprocessor Systems with
Parallel-Pipelined Memories (F.A. Briggs and M. Dubois).
On the Validity of Trace-Driven Simulation for Multiprocessors
(E.J. Koldinger, S.J. Eggers, and H.M. Levy).
Multiprocessor Cache Simulation Using Hardware Collected Address
Traces (A.W. Wilson).
Cache Invalidation Patterns in Shared-Memory Multiprocessors (A.
Gupta and W.-D. Weber).
Benchmark Characterization for Experimental System Evaluation (T.M.
Conte and W.W. Hwu).
A Model of Workloads and Its Use in Miss-Rate Prediction for Fully
Associative Caches (J.P. Singh. H.S. Stone, and D.F.
Thiebaut).
Chapter 5: Performance Evaluation Studies of Software Coherence
Schemes).
A Performance Comparison of Directory-Based and Timestamp-Based
Cache Coherence Schemes (S.L. Min and J.-L. Baer).
Evaluating the Performance of Software Cache Coherence (S. Owicki
and A. Agarwal).
Comparison of Hardware and Software Cache Coherence Schemes (S.V.
Adve, V.S. Adve, M.D. Hill, and M.K. Vernon).
About the Author.
Engineering, Schools of Electrical Engineering, University of
Belgrade. He received the BSEE in 1984 and MSEE in 1989, both from
the School of Electrical Engineering, University of Belgrade,
Belgrade, Serbia, Yugoslavia. He is in the final phase of finishing
his PhD thesis on dynamic software maintenance of cache coherence
in shared-memory multiprocessors. From 1984 to 1989 he was with the
Laboratory for Computer Engineering, Institute for Nuclear
Sciences, Vinca, Serbia, Yugoslavia, working primarily on the
development of a real-time computer for applications in biophysics
and distributed operating system for a special-purpose
multicomputer. His current research interests include
multiprocessor and multicomputer architectures, heterogeneous
processing, and system software support for shared-memory
multiprocessors and distributed systems.
Veljko Milutinovic has been the Department of Computer Engineering,
Schools of Electrical Engineering, University of Belgrade,
Belgrade, Serbia Yugoslavia since 1990. From 1982 to 1990 he was on
the faculty of the School of Electrical and Computer Engineering,
Purdue University, West Lafayette, Indiana. He has been active in
the RISC field for the last decade and in technology-related
research (32-bit GaAS RISC for RCA) and application-related
research (multimedia-oriented RISC-based multiprocessors efforts of
NCR). He has published 40 papers in IEEE journals and presented
over 200 invited talks all over the world. He is a senior member of
the IEEE.
