System Level ESD Co-Design
Wiley - IEEE
1. Auflage September 2015
424 Seiten, Hardcover
Wiley & Sons Ltd
An effective and cost efficient protection of electronic system against ESD stress pulses specified by IEC 61000-4-2 is paramount for any system design. This pioneering book presents the collective knowledge of system designers and system testing experts and state-of-the-art techniques for achieving efficient system-level ESD protection, with minimum impact on the system performance. All categories of system failures ranging from 'hard' to 'soft' types are considered to review simulation and tool applications that can be used.
The principal focus of System Level ESD Co-Design is defining and establishing the importance of co-design efforts from both IC supplier and system builder perspectives. ESD designers often face challenges in meeting customers' system-level ESD requirements and, therefore, a clear understanding of the techniques presented here will facilitate effective simulation approaches leading to better solutions without compromising system performance.
With contributions from Robert Ashton, Jeffrey Dunnihoo, Micheal Hopkins, Pratik Maheshwari, David Pomerenke, Wolfgang Reinprecht, and Matti Usumaki, readers benefit from hands-on experience and in-depth knowledge in topics ranging from ESD design and the physics of system ESD phenomena to tools and techniques to address soft failures and strategies to design ESD-robust systems that include mobile and automotive applications.
The first dedicated resource to system-level ESD co-design, this is an essential reference for industry ESD designers, system builders, IC suppliers and customers and also Original Equipment Manufacturers (OEMs).
Key features:
* Clarifies the concept of system level ESD protection.
* Introduces a co-design approach for ESD robust systems.
* Details soft and hard ESD fail mechanisms.
* Detailed protection strategies for both mobile and automotive applications.
* Explains simulation tools and methodology for system level ESD co-design and overviews available test methods and standards.
* Highlights economic benefits of system ESD co-design.
Charvaka Duvvury
Chapter 2 Component Versus System Level ESD
Charvaka Duvvury and Harald Gossner
Chapter 3 System Level Testing for ESD Susceptibility
Michael Hopkins
Chapter 4 PCB/IC Co-Design Concepts for SEED
Harald Gossner and Charvaka Duvvury
Chapter 5 Hard Fails & PCB Protection Devices
Robert Ashton
Chapter 6 Soft Fail and PCB design measures
David Pommerenke and Pratik Maheshwari
Chapter 7 ESD in Mobile Devices
Matti Uusimäki
Chapter 8 ESD for Automotive Applications
Wolfgang Reinprecht
Chapter 9 Futire Applications of SEED Methodology
Harald Gossner and Charvaka Duvvury
Chapter 10 Co-Design Tradeoffs: Balancing Robustness, Performance and Cost
Jeffery C. Dunnihoo
Index
Passi Tamminen, EMC Specialist at Microsoft, Finland
Charvaka Duvvury, formerly of Texas Instruments, is currently working as a technical consultant on ESD design methods and ESD qualification support. He has published over 150 technical papers and holds more than 70 patents. He is a co-founder and co-chair of the Industry Council on ESD Target Levels and has been serving as Board of Director of the ESDA since 1997 promoting university education and research in ESD technology.
Harald Gossner, Intel, Germany
Harald Gossner is Senior Principal Engineer at Intel where for 15 years he has worked on the development of ESD protection concepts with Siemens and Infineon Technologies. In 2010 he has joined Intel Mobile Communications overseeing the development of robust mobile systems. Harald has authored and co-authored more than 100 technical papers and one book in the field of ESD and device physics. He holds more than 60 patents on the same topic. In 2006 he became cofounder and co-chair of the Industry Council on ESD Target Levels.
