Advanced Interconnects for ULSI Technology
1. Edition March 2012
606 Pages, Hardcover
Handbook/Reference Book
Short Description
Advanced Interconnects for ULSI Technology is dedicated to the materials and methods which might be suitable replacements. It covers a broad range of topics, from physical principles to design, fabrication, characterization, and application of new materials for nano-interconnects.
Finding new materials for copper/low-k interconnects is critical to the continuing development of computer chips. While copper/low-k interconnects have served well, allowing for the creation of Ultra Large Scale Integration (ULSI) devices which combine over a billion transistors onto a single chip, the increased resistance and RC-delay at the smaller scale has become a significant factor affecting chip performance.
Advanced Interconnects for ULSI Technology is dedicated to the materials and methods which might be suitable replacements. It covers a broad range of topics, from physical principles to design, fabrication, characterization, and application of new materials for nano-interconnects, and discusses:
* Interconnect functions, characterisations, electrical properties and wiring requirements
* Low-k materials: fundamentals, advances and mechanical properties
* Conductive layers and barriers
* Integration and reliability including mechanical reliability, electromigration and electrical breakdown
* New approaches including 3D, optical, wireless interchip, and carbon-based interconnects
Intended for postgraduate students and researchers, in academia and industry, this book provides a critical overview of the enabling technology at the heart of the future development of computer chips.
List of Contributors xvii
Preface xxi
List of Abbreviations xxv
Section I Low-k Materials 1
1 Low-k Materials: Recent Advances 3
Geraud Dubois and Willi Volksen
1.1 Introduction 3
1.2 Integration Challenges 5
1.3 Processing Approaches to Existing Integration Issues 10
1.4 Material Advances to Overcome Current Limitations 16
1.5 Conclusion 22
2 Ultra-Low-k by CVD: Deposition and Curing 35
Vincent Jousseaume, Aziz Zenasni, Olivier Gourhant, Laurent Favennec and Mikhail R. Baklanov
2.1 Introduction 35
2.2 Porogen Approach by PECVD 37
2.3 UV Curing 42
2.4 Impact of Curing on Structure and Physical Properties: Benefits of UV Curing 49
2.5 Limit/Issues with the Porogen Approach 57
2.6 Future of CVD Low-k 62
2.7 Material Engineering: Adaptation to Integration Schemes 68
2.8 Conclusion 70
3 Plasma Processing of Low-k Dielectrics 79
Hualing Shi, Denis Shamiryan, Jean-Francois de Marneffe, Huai Huang, Paul S. Ho and Mikhail R. Baklanov
3.1 Introduction 79
3.2 Materials and Equipment 80
3.3 Process Results Characterization 82
3.4 Interaction of Low-k Dielectrics with Plasma 85
3.5 Mechanisms of Plasma Damage 92
3.6 Dielectric Recovery 112
3.7 Conclusions 121
4 Wet Clean Applications in Porous Low-k Patterning Processes 129
Quoc Toan Le, Guy Vereecke, Herbert Struyf, Els Kesters and Mikhail R. Baklanov
4.1 Introduction 129
4.2 Silica and Porous Hybrid Dielectric Materials 130
4.3 Impact of Plasma and Subsequent Wet Clean Processes on the Stability of Porous Low-k Dielectrics 134
4.4 Removal of Post-Etch Residues and Copper Surface Cleaning 141
4.5 Plasma Modification and Removal of Post-Etch 193 nm Photoresist 146
Section II Conductive Layers and Barriers 173
5 Copper Electroplating for On-Chip Metallization 175
Valery M. Dubin
5.1 Introduction 175
5.2 Copper Electroplating Techniques 176
5.3 Copper Electroplating Superfill 177
5.4 Alternative Cu Plating Methods 182
5.5 Electroplated Cu Properties 184
5.6 Conclusions 186
6 Diffusion Barriers 193
Michael Hecker and René Hübner
6.1 Introduction 193
6.2 Metal-Based Barriers as Liners for Cu Seed Deposition 198
6.3 Advanced Barrier Approaches 212
6.4 Conclusions 221
Section III Integration and Reliability 235
7 Integration and Electrical Properties 237
Sridhar Balakrishnan, Ruth Brain and Larry Zhao
7.1 Introduction 237
7.2 On-Die Interconnects in the Submicrometer Era 237
7.3 On-Die Interconnects at Sub-100 nm Nodes 240
7.4 Integration of Low-k Dielectrics in Sub-65 nm Nodes 241
7.5 Patterning Integration at Sub-65 nm Nodes 248
7.6 Integration of Conductors in Sub-65 nm Nodes 252
7.7 Novel Air-Gap Interconnects 258
8 Chemical Mechanical Planarization for Cu-Low-k Integration 267
Gautam Banerjee
8.1 Introduction 267
8.2 Back to Basics 268
8.3 Mechanism of the CMP Process 268
8.4 CMP Consumables 271
8.5 CMP Interactions 276
8.6 Post-CMP Cleaning 281
8.7 Future Direction 287
References 288
9 Scaling and Microstructure Effects on Electromigration Reliability for Cu Interconnects 291
Chao-Kun Hu, René Hübner, Lijuan Zhang, Meike Hauschildt and Paul S. Ho
9.1 Introduction 291
9.2 Electromigration Fundamentals 293
9.3 Cu Microstructure 300
9.4 Lifetime Enhancement 306
9.5 Effect of Grain Size on EM Lifetime and Statistics 321
9.6 Massive-Scale Statistical Study of EM 326
9.7 Summary 329
10 Mechanical Reliability of Low-k Dielectrics 339
Kris Vanstreels, Han Li and Joost J. Vlassak
10.1 Introduction 339
10.2 Mechanical Properties of Porous Low-k Materials 340
10.3 Fracture Properties of Porous Low-k Materials 352
10.4 Conclusion 361
11 Electrical Breakdown in Advanced Interconnect Dielectrics 369
Ennis T. Ogawa and Oliver Aubel
11.1 Introduction 369
11.2 Reliability Testing 378
11.3 Lifetime Extrapolation and Models 397
11.4 Future Trends and Concerns 403
Section IV New Approaches 435
12 3D Interconnect Technology 437
John U. Knickerbocker, Lay Wai Kong, Sven Niese, Alain Diebold and Ehrenfried Zschech
12.1 Introduction 437
12.2 Dimensional Interconnected Circuits (3DICs) for System Applications 438
John U. Knickerbocker
12.3 Advanced Microscopy Techniques for 3D Interconnect Characterization 467
Lay Wai Kong, Sven Niese, Alain Diebold and Ehrenfried Zschech
12.4 Summary 486
13 Carbon Nanotubes for Interconnects 491
Mizuhisa Nihei, Motonobu Sato, Akio Kawabata, Shintaro Sato and Yuji Awano
13.1 Introduction 491
13.2 Advantage of CNT Vias 492
13.3 Fabrication Processes of CNT Vias 493
13.4 Electrical Properties of CNT Vias 496
13.5 Current Reliability of CNT Vias 498
13.6 Conclusion 501
14 Optical Interconnects 503
Wim Bogaerts
14.1 Introduction 503
14.2 Optical Links 505
14.3 The Case for Silicon Photonics 519
14.4 Optical Networks on a Chip 528
14.5 Integration Strategies 532
14.6 Conclusion 538
15 Wireless Interchip Interconnects 543
Takamaro Kikkawa
15.1 Introduction 543
15.2 Wireless Interconnect Technologies 547
15.3 Conclusion 561
References 561
Index
